? semiconductor components industries, llc, 2015 february, 2015 ? rev. 9 1 publication order number: mc74ac373/d mc74ac373, mc74act373 octal transparent latch with 3-state outputs the mc74ac373/74act373 consists of eight latches with 3?state outputs for bus organized system applications. the flip?flops appear transparent to the data when latch enable (le) is high. when le is low, the data that meets the setup time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the bus output is in the high impedance state. features ? eight latches in a single package ? 3?state outputs for bus interfacing ? outputs source/sink 24 ma ? act373 has ttl compatible inputs ? these are pb?free devices figure 1. pinout: 20?lead packages conductors (top view) 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 le oe o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd pin assignment pin function d 0 ?d 7 data inputs le latch enable input oe output enable input o 0 ?o 7 3?state latch outputs figure 2. logic symbol o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 le oe www. onsemi.com soic?20w dw suffix case 751d tssop?20 dt suffix case 948e 1 1 see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information see general marking information in the device marking section on page 9 of this data sheet. device marking information
mc74ac373, mc74act373 www. onsemi.com 2 truth table inputs outputs oe le d n o n h x x z l h l l l h h h l l x o 0 h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = previous o 0 before low-to-high transition of clock functional description the mc74ac373/74act373 contains eight d?type latches with 3?state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low, the latches store the information that was present on the d inputs a setup time preceding the high?to?low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2?state mode. when oe is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. figure 3. logic diagram d g o d g o d g o d g o d g o d g o d g o d g o d 1 d 2 d 3 d 4 d 5 d 6 d 7 le oe d 0 note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
mc74ac373, mc74act373 www. onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) (note 1) ?0.5 to v cc +0.5 v i ik dc input diode current 20 ma i ok dc output diode current 50 ma i out dc output sink/source current 50 ma i cc dc supply current, per output pin 50 ma i gnd dc ground current, per output pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 140 c ja thermal resistance (note 2) soic tssop 65.8 110.7 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) > 2000 > 200 > 1000 v i latchup latchup performance above v cc and below gnd at 85 c (note 6) 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. i out absolute maximum rating must be observed. 2. the package thermal impedance is calculated in accordance with jesd 51?7. 3. tested to eia/jesd22?a114?a. 4. tested to eia/jesd22?a115?a. 5. tested to jesd22?c101?a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v act 4.5 5.0 5.5 v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v t r , t f input rise and fall time (note 7) ac devices except schmitt inputs v cc @ 3.0 v ? 150 ? v cc @ 4.5 v ? 40 ? ns/v v cc @ 5.5 v ? 25 ? t r , t f input rise and fall time (note 8) act devices except schmitt inputs v cc @ 4.5 v ? 10 ? ns/v v cc @ 5.5 v ? 8.0 ? t a operating ambient temperature range ?40 25 85 c i oh output current ? high ? ? ?24 ma i ol output current ? low ? ? 24 ma functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 7. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 8. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac373, mc74act373 www. onsemi.com 4 dc characteristics symbol parameter v cc (v) 74ac 74ac unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 3.0 1.5 2.1 2.1 v out = 0.1 v 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 1.5 0.9 0.9 v out = 0.1 v 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 2.99 2.9 2.9 i out = ?50 a 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v *v in = v il or v ih 3.0 ? 2.56 2.46 ?12 ma 4.5 ? 3.86 3.76 i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 3.0 0.002 0.1 0.1 i out = 50 a 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v *v in = v il or v ih 3.0 ? 0.36 0.44 12 ma 4.5 ? 0.36 0.44 i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i oz maximum 3?state current v i (oe) = v il , v ih 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac373, mc74act373 www. onsemi.com 5 ac characteristics (for figures and waveforms ? see and8277/d at www.onsemi.com) symbol parameter v cc * (v) 74ac 74ac unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max t plh propagation delay 3.3 1.5 10 13.5 1.5 15 ns 3?5 d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 t phl propagation delay 3.3 1.5 9.5 13 1.5 14.5 ns 3?5 d n to o n 5.0 1.5 7.0 9.5 1.5 10.5 t plh propagation delay 3.3 1.5 10 13.5 1.5 15 ns 3?6 le to o n 5.0 1.5 7.5 9.5 1.5 10.5 t phl propagation delay 3.3 1.5 9.5 12.5 1.5 14 ns 3?6 le to o n 5.0 1.5 7.0 9.5 1.5 10.5 t pzh output enable time 3.3 1.5 9.0 11.5 1.0 13 ns 3?7 5.0 1.5 7.0 8.5 1.0 9.5 t pzl output enable time 3.3 1.5 8.5 11.5 1.0 13 ns 3?8 5.0 1.5 6.5 8.5 1.0 9.5 t phz output disable time 3.3 1.5 10 12.5 1.0 14.5 ns 3?7 5.0 1.5 8.0 11 1.0 12.5 t plz output disable time 3.3 1.5 8.0 11.5 1.0 12.5 ns 3?8 5.0 1.5 6.5 8.5 1.0 10 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements symbol parameter v cc * (v) 74ac 74ac unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low 3.3 3.5 5.5 6.0 ns 3?9 d n to le 5.0 2.0 4.0 4.5 t h hold time, high or low 3.3 ?3.0 1.0 1.0 ns 3?9 d n to le 5.0 ?1.5 1.0 1.0 t w le pulse width, high 3.3 4.0 5.5 6.0 ns 3?6 5.0 2.0 4.0 4.5 *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac373, mc74act373 www. onsemi.com 6 dc characteristics symbol parameter v cc (v) 74act 74act unit conditions t a = +25 c t a = ?40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 4.5 1.5 2.0 2.0 v v out = 0.1 v 5.5 1.5 2.0 2.0 or v cc ? 0.1 v v il maximum low level input voltage 4.5 1.5 0.8 0.8 v v out = 0.1 v 5.5 1.5 0.8 0.8 or v cc ? 0.1 v v oh minimum high level output voltage 4.5 4.49 4.4 4.4 v i out = ?50 a 5.5 5.49 5.4 5.4 *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ?24 ma 5.5 ? 4.86 4.76 ?24 ma v ol maximum low level output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i oz maximum 3-state current v i (oe) = v il , v ih 5.5 ? 0.5 5.0 a v i = v cc , gnd v o = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ?75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time.
mc74ac373, mc74act373 www. onsemi.com 7 ac characteristics (for figures and waveforms ? see and8277/d at www.onsemi.com) symbol parameter v cc * (v) 74act 74act unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf min typ max min max t plh propagation delay d n to o n 5.0 2.5 8.5 10 1.5 11.5 ns 3?5 t phl propagation delay d n to o n 5.0 2.0 8.0 10 1.5 11.5 ns 3?5 t plh propagation delay le to o n 5.0 2.5 8.5 11 2.0 11.5 ns 3?6 t phl propagation delay le to o n 5.0 2.0 8.0 10 1.5 11.5 ns 3?6 t pzh output enable time 5.0 2.0 8.0 9.5 1.5 10.5 ns 3?7 t pzl output enable time 5.0 2.0 7.5 9.0 1.5 10.5 ns 3?8 t phz output disable time 5.0 2.5 9.0 11 2.5 12.5 ns 3?7 t plz output disable time 5.0 1.5 7.5 8.5 1.0 10 ns 3?8 *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements (for figures and waveforms ? see and8277/d at www.onsemi.com) symbol parameter v cc * (v) 74act 74act unit fig. no. t a = +25 c c l = 50 pf t a = ?40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low d n to le 5.0 3.0 7.0 8.0 ns 3?9 t h hold time, high or low d n to le 5.0 0 0 1.0 ns 3?9 t w le pulse width, high 5.0 2.0 7.0 8.0 ns 3?6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v
mc74ac373, mc74act373 www. onsemi.com 8 ordering information device package shipping ? mc74ac373dwg soic?20 (pb?free) 38 units / rail MC74AC373DWR2G soic?20 (pb?free) 1000 / tape & reel mc74act373dwg soic?20 (pb?free) 38 units / rail mc74act373dwr2g soic?20 (pb?free) 1000 / tape & reel mc74ac373dtg tssop?20 (pb?free) 75 units / rail mc74ac373dtr2g tssop?20 (pb?free) 2500 / tape & reel mc74act373dtg tssop?20 (pb?free) 75 units / rail mc74act373dtr2g tssop?20 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. marking diagrams soic?20w tssop?20 1 20 ac 373 alyw a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package (note: microdot may be in either location) 1 20 act 373 alyw 20 1 act373 awlyywwg 20 1 ac373 awlyywwg
mc74ac373, mc74act373 www. onsemi.com 9 package dimensions tssop?20 dt suffix case 948e?02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. 110 11 20 pin 1 ident a b ?t? 0.100 (0.004) c d g h section n?n k k1 jj1 n n m f ?w? seating plane ?v? ?u? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mc74ac373, mc74act373 www. onsemi.com 10 package dimensions soic?20w dw suffix case 751d?05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74ac373/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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